![\"stopwatch\"](\"https:\/\/antonpotocnik.com\/wp-content\/uploads\/2016\/10\/stopwatch-300x200.jpg\")
<\/p>\nIn this Red Pitaya FPGA project we will learn about communication between the Linux processing system and the programmable logic. We will demonstrate the basic functionality with a simple FPGA project – Stopwatch.<\/p>\n
<\/p>\n
The FPGA algorithm will be based on a 32-bit binary counter with Clock Enable (CE) and Synchronous Clear (SCLR) inputs which we will control from the Linux side. The counter’s output value we will be read with a Linux program and partially displayed with the on-board LEDs. In order to do this we will use standard AXI communication protocol<\/a> that connects different parts on the Zynq device such as processing system, programmable logic, DDR memory, external peripherals and more.<\/p>\n To build Stopwatch project in Vivado you can either download the project’s tcl script from the github<\/a> as described in the first post<\/a> or simply go through the following steps. This guide assumes that you are familiar with the concepts introduced in the previous two posts.<\/p>\n Open one of the previous Vivado projects to get a basic block diagram. Next, insert the binary counter, if it is not already present, and add CE and SCLR ports. This can be done by double-clicking on the binary counter IP core in our block design and select CE and SCLR under the Control tab. Then add xlslice<\/em> IP block with Din Width<\/em>: 32, Din From<\/em>: 31, Din Down To<\/em>: 24. Connect CLK pin of the binary counter to PS’s FCLK_CLK0<\/em>, output of the binary counter to the input of the xlslice<\/em> and output of the xlslice<\/em> to led_o<\/em> external port. This last part will display 8 MSBs of the 32-bit counter on Red Pitaya’s LED bar. If you started from Project 1 change the LEFT property of led_o<\/em> port from 0 to 7.<\/p>\n We are ready to insert AXI General Purpose IO IP core (AXI GPIO<\/em>) to our block design. When the core is added, double-click on the block, check Enable Dual Channel<\/em> and set All Inputs<\/em> for the GPIO 2. To connect the AXI GPIO to the processing system click on Run Connection Automation<\/em> on top of the block design. Select S_AXI<\/em> and click OK. This will automatically create AXI Interconnect<\/em> and Processor System Reset<\/em> blocks. Next, add two xlslice IP cores with 32-bit Din. xls_CE<\/em> should have Din From<\/em> and Din Down To<\/em> both set to 0 and xls_SCLR<\/em> should have them both set to 1. Connect all the blocks as shown in the figure below.<\/p>\n Next, we need to set the AXI GPIO core’s memory address and range. We will use this address later to access the IP core from the Linux side. On top of the window choose Address Editor tab and set all the values as shown below. Remember the address of our GPIO block is 0x4200_0000.<\/p>\n The FPGA program is ready. Proceed with synthesis, implementation and generate the bitstream file. When the file is generated and copied to a folder on Red Pitaya’s Linux write the bitstream file to programmable logic with the following command<\/p>\n To write or read from our FPGA program we will use Red Pitaya’s monitor<\/a> tool available in the Red Pitaya’s Linux. Try the following commands.<\/p>\n Great, we have created a stopwatch with a resolution of 8 ns! Using AXI communication protocol we can easily access our GPIO IP core. More details about the GPIO core can be found in the references part of this post.<\/p>\n If you would like to know how much time has passed between start and stop in seconds and not in the number of clock cycles, you can use the following program on Linux to write, read and convert data. This program, based on Pavel Demin’s code<\/a>, can also be a useful template for more advanced applications where you need to set several parameters and read large amount of data generated on FPGA.<\/p>\n stopwatch.c:<\/p>\n stopwatch.c program maps the memory at a given address to cfg<\/em> pointer. By writing an appropriate 32-bit value to this pointer the code first clears the counter by setting SCLR (2nd bit), then starts the count by setting CE (1st bit). After wait_time<\/em> in seconds the program stops the counter by clearing the CE bit. To read counter’s output value we need to access the second port of the GPIO IP core. According to GPIO documentation<\/a> the address of the second port is shifted by 8 (0x4200_0008). At the end the counter output value is scaled by the FCLK_CLK0 frequency and printed on the screen.<\/p>\n Compile and execute the program as shown here.<\/p>\n Interestingly, FCLK_CLK0<\/em> has a frequency of 124.99875 MHz (= 3.75*33.333 MHz). This is a default Red Pitaya frequency generated by IO PLL<\/a> using 33.333 MHz external clock (PS_CLK<\/a>). To increase the frequency to, for example, 143 MHz use the bash script mentioned by Jean in the comments.<\/p>\n In conclusion, we have created another simple project where we learned how to communicate between our FPGA program and Linux running on Red Pitaya’s Zynq7 ARM processor. Armed with this knowledge we can now move to more serious projects such as high-speed ADC averager for heterodyne detection or lock-in amplification. Coming soon.<\/p>\n![\"stopwatch_diagram\"](\"https:\/\/antonpotocnik.com\/wp-content\/uploads\/2016\/11\/stopwatch_diagram.png\")
<\/a><\/p>\n![\"3_stopwatch_addresses\"](\"https:\/\/antonpotocnik.com\/wp-content\/uploads\/2016\/10\/3_stopwatch_Addresses.png\")
<\/a><\/p>\n\r\ncat system_wrapper.bit > \/dev\/xdevcfg\r\n<\/pre>\n
\r\nmonitor 0x42000000 1 # write: start, SCLR = 0, CE = 1\r\nmonitor 0x42000000 0 # write: stop, SCLR = 0, CE = 0\r\nmonitor 0x42000000 2 # write: clear, SCLR = 1, CE = 0\r\n\r\nmonitor 0x42000000 # read: cfg on GPIO1\r\nmonitor 0x42000008 # read: data on GPIO2\r\n<\/pre>\n
\r\n#include <stdio.h>\r\n#include <stdint.h>\r\n#include <unistd.h>\r\n#include <sys\/mman.h>\r\n#include <fcntl.h>\r\n#include <stdlib.h>\r\n\r\nint main(int argc, char **argv)\r\n{\r\n int fd;\r\n float wait_time;\r\n uint32_t count;\r\n void *cfg;\r\n char *name = "\/dev\/mem";\r\n const int freq = 124998750; \/\/ Hz\r\n\r\n if (argc == 2) wait_time = atof(argv[1]);\r\n else wait_time = 1.0;\r\n\r\n if((fd = open(name, O_RDWR)) < 0) {\r\n perror("open");\r\n return 1;\r\n }\r\n cfg = mmap(NULL, sysconf(_SC_PAGESIZE), \/* map the memory *\/\r\n PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x42000000);\r\n\r\n *((uint32_t *)(cfg + 0)) = 2; \/\/ clear timer\r\n *((uint32_t *)(cfg + 0)) = 1; \/\/ start timer\r\n\r\n sleep(wait_time); \/\/ wait for [wait_time] seconds\r\n\r\n *((uint32_t *)(cfg + 0)) = 0; \/\/ stop timer\r\n\r\n count = *((uint32_t *)(cfg + 8)); \/\/ get binary counter output\r\n\r\n printf("Clock count: %5d, calculated time: %5f s\\n", \r\n count, (double)count\/freq);\r\n\r\n munmap(cfg, sysconf(_SC_PAGESIZE));\r\n return 0;\r\n}\r\n<\/pre>\n\r\ngcc -o stopwatch stopwatch.c\r\n.\/stopwatch 5 # wait for 5 s\r\n<\/pre>\n